To improve bit density of nonvolatile semiconductor storage devices such as NAND-type flash memory, etc., because miniaturization technology has come close to its limits, stacking of memory cells has become a promising option. As one such example, a stacked NAND-type flash memory in which vertical transistors make up the memory transistor has been proposed. The stacked NAND-type flash memory includes a memory string that is made up of multiple memory transistors that are serially connected in the stacked direction, and select transistors that are installed on both ends of that memory string.
In conventional designs, however, the adjustment of the threshold voltage of the select transistor is not sufficiently done, and the breadth of the threshold voltage distribution is large. Thus, it has not been possible to sufficiently control the performance of select transistors.